1. Field of Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, to an improved FinFET formed on a semiconductor substrate.
2. Description of Prior Art
One important trend in the integrated circuits is scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) so as to achieve a high integration degree of devices and reduce the manufacturing costs. However, it is well known that short channel effect occurs with reducing the gate length of the MOSFET. When the size of the MOSFET is reduced, the gate of the MOSFET has a smaller effective gate length and actually, comparing a long gate length MOSFET, controls less charges in a depletion region with a given gate voltage, and the MOSFET has a reduced threshold voltage with a reduced channel length.
A conventional planar MOSFET has a tri-layer structure including a gate electrode, a semiconductor layer, and a gate dielectric sandwiched therebetween. A channel region is provided in the semiconductor layer below the gate electrode, and source/drain regions are provided in the semiconductor layer adjacent to and at two opposing sides of the channel region. A silicide layer may be provided on the source/drain regions and then coupled with source/drain electrodes through vias so as to reduce the parasitic resistance of the device. The planar MOSFET suffers from the short channel effect and has a threshold voltage fluctuating with variation of the channel length.
To suppress the short channel effect, U.S. Pat. No. 6,413,802 discloses a FinFET formed on a SOI substrate, comprising a channel region provided in the central portion of a fin of semiconductive material and source/drain regions provided at two ends of the fin. Gate electrodes are provided at both sides of the channel region and surround the latter to provide for example a double gate FinFET. Inversion channels are induced in the fin at both sides of the gate. The channel region in the fin has a small thickness so that the whole channel region is controlled by the gate, as a result of which, the short channel effect is suppressed.
However, in a conventional FinFET, the gate is provided between the source and the drain regions and extends parallel thereto. Since the distance between the source/drain regions and the gate is typically small enough for a capacitive couple introduced therebetween, the resultant device has a large parasitic resistance and capacitance.
Moreover, the capacitive coupling between the source/drain regions and the gate limits the freedom of device design. For example, if one attempts to reduce a parasitic resistance, the thickness of the source/drain regions should be increased.
However, the source/drain regions having a larger thickness also means an increased coupling area between the source/drain regions and the gate, which in turn causes the parasitic capacitance to increase, or vice versa. Thus, one skilled person in the art can not reduce both of the parasitic resistance and the parasitic capacitance together in a conventional FinFET.
Consequently, the conventional FinFET has a delay due to a large value of the time constant RC and thus has a low switching speed.
Moreover, the FinFET formed on a SOI has the disadvantage of having a much higher manufacturing costs than that of a FinFET formed on a bulk semiconductor substrate.